Hole Design Standard – Potential Conflict with Via Copper Area

Reason for Failed Review:

Some holes in your design overlap or cut into the copper area of vias, making it unclear whether this is intentional.

If not handled properly, this could cause open circuits, exposed copper, or plating issues during manufacturing.

PCBasic Suggestions:

1. If the vias are not required, please delete them directly in your design to avoid unnecessary overlap.

2. If the vias are intended to remain, please maintain a minimum spacing of 0.2 mm between the holes and nearby vias or copper areas to ensure electrical and mechanical reliability.

Following this design rule helps PCBasic ensure precise drilling, stable plating, and high-quality board performance.